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Three examples in XiperPy vs. its alternatives

A counter, a FIFO, and a traffic-light controller written in XiperPy and the usual alternatives. The examples show what changes when hardware starts as Python instead of HDL or Scala.

The minimal example. A synchronous counter with reset. The smallest unit that still shows the round-trip from declaration to clocked behaviour.

counter.py
XiperPy
from xiperpy import Entity, Unsigned, process

class Counter(Entity):
    count: Unsigned[8] = 0

    @process
    def tick(self):
        self.count += 1
counter.v
Verilog
module counter (
    input            clk,
    input            rst_n,
    output reg [7:0] count
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) count <= 8'd0;
        else        count <= count + 1'b1;
    end
endmodule

One language for the whole hardware loop

Software teams work in one productive ecosystem from idea to test to deployment. XiperPy brings that model to hardware: design, generation, simulation, and verification stay in Python, while Verilog and VHDL remain readable implementation outputs.

XiperPy: native Python HDL workflow
  1. Hardware design
  2. Behavior testing
  3. RTL verification
  4. HDL emission
    • Define I/O
    • Specify logic
    • Create parameter sets
    • Automated generation
    • Property checks
    • Equivalence proofs
    • Readable Verilog
    • Readable VHDL
Iterate without leaving Python
  • Verilog
  • VHDL

Prior art

Who needs another HDL?

Teams whose value is in custom IP — and who need a faster way to design, generate, simulate, test, and emit readable VHDL and Verilog.

Tool
Language
Lines
HDL Targets
Python-Native

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