Develop hardware like software

Write Python.
Generate hardware.

XiperPy — a Python-to-HDL compiler.

The distance from Python to hardware has never been shorter

The dominant hardware description languages are from the 1980s. Newer tools have raised the abstraction level, but designing hardware still means leaving the software ecosystem behind — different languages, different toolchains, different workflows.

XiperPy changes the entry point. Hardware concepts — entities, signals, clocked processes — are expressed through Python classes, decorators, and operators. The concepts are new. The syntax isn't.

We started Xiper to make hardware development feel native to the tools and workflows that software engineers already use.

Python native

Classes, decorators, operator overloading. Hardware expressed through patterns you already know.

Developer first

pip install. Your editor. Your terminal. No vendor toolchain required to start.

Collaborative

Git-native, reviewable, composable. Hardware that lives in a codebase.

Hardware at software speed

Generate synthesizable VHDL and Verilog without leaving your Python workflow.

Seeing is believing

One counter. Six toolchains.

An 8-bit counter with a clocked increment. The same design, implemented in every relevant Python HDL toolchain — and XiperPy.

XiperPy

from xiperpy import Entity, Unsigned, process

class Counter(Entity):
    count = Unsigned.field(8)

    @process
    def increment(self):
        self.count << self.count + 1

Amaranth

from amaranth import *

class Counter(Elaboratable):
    def elaborate(self, platform):
        m = Module()
        count = Signal(8)
        m.d.sync += count.eq(count + 1)
        return m

Get early access to XiperPy

We're opening XiperPy to a small group of engineers and teams who want to shape the tool as it develops. You get the compiler, direct support, and influence over the roadmap.

Request Early Access

The road ahead

Horizon 1

Python to HDL

Write hardware designs in Python. Generate synthesizable VHDL and Verilog. Simulate with GHDL and Verilator. This is what early access delivers — a pip-installable compiler that takes Python in and emits HDL out.

Horizon 2

The full toolchain

Import existing VHDL, Verilog, and C++ into XiperPy projects. All sources compile to a shared intermediate representation for simulation and verification. Emit HDL from mixed-language designs. IDE integration with linting and language server support for VS Code.

Horizon 3

Collaborative hardware development

XiperPy in the browser. Edit designs collaboratively in real time. Stream simulation results as you type. Hardware development with the same workflow your team already uses for software.

Write Python.Generate hardware.