XiperPy
The complete hardware design toolchain — not a limited subset, not a trial. The full pipeline from source ingestion through simulation, verification, and HDL emission.
Ingest Any Source
Read Python, C++, VHDL, and Verilog sources. All inputs converge into a unified intermediate representation for analysis and transformation.
Simulate & Verify
Run cycle-accurate simulation on your designs and verify correctness against your original sources — before committing to silicon.
Emit HDL
Generate synthesizable Verilog and VHDL targeting FPGA and ASIC flows. The output integrates with standard EDA toolchains.
Features
Python-First Design
Define hardware as Python classes with typed signals and @process decorators. XiperPy generates synthesizable Verilog, SystemVerilog, or VHDL from the same source.
Cycle-Accurate Simulation
Simulate designs cycle-by-cycle with a deterministic two-phase tick model. Read signals, schedule assignments, and verify behavior — all in Python.
Visual Placement
Visualize component placement and routing. Understand your design's physical layout as you build it.
Collaborative
Work together in real time. Share designs, review changes, and build hardware as a team — all in the browser.
Full Generation Pipeline
Go from Python to HDL. XiperPy analyzes your @process methods, builds a target-independent IR, and emits Verilog, SystemVerilog, or VHDL.
Built for Teams
From students learning hardware design to experienced FPGA teams shipping production silicon. XiperPy scales with you.