VHDL. Verilog.
Write Python.
Generate hardware.

XiperPy is an open-source Python-based hardware design language. Describe digital logic in Python, simulate and verify in pytest, emit synthesizable VHDL and Verilog for your existing FPGA toolchain.

example.py

XiperPy

from xiperpy import Entity, Unsigned, process

class Counter(Entity):
    count = Unsigned.field(8)

    @process
    def increment(self):
        self.count << self.count + 1

example.v

Verilog

module counter (
    input  wire       clk,
    output reg [7:0]  count
);
    always @(posedge clk)
        count <= count + 1;
endmodule

Design

Describe hardware in Python.

Define hardware as Python classes with typed signals and @process methods. The same Python source describes the digital logic and serves as the artifact your software team can read — no second source of truth, no rewrite per HDL, no detour through a separate hardware description language.

Simulate

Run simulation in Python.

Run cycle-accurate simulation through GHDL or Verilator without leaving Python. Drive stimulus from numpy and pandas — feed real workloads, captured traces, or synthesized data straight into your design. Edit a test, re-run pytest, see the result.

Verify

Verify with the Python ecosystem.

Express invariants like FIFO never overflows below capacity or output is monotonic and let Hypothesis search for the input that breaks them. Test benches stay in Python, run as a normal pytest suite, and gate your hardware changes through the same CI you already use for software — one pipeline, one report.

Emit

Drop into your EDA flow.

Generate synthesizable VHDL and Verilog from the same Python module. The output is plain text, drops into the standard EDA toolchain you use today, and targets whichever HDL flow your FPGA expects. XiperPy stays out of the back end.

The road ahead

Horizon 1

Python to HDL

Write hardware designs in Python. Generate synthesizable VHDL and Verilog. Simulate with GHDL and Verilator. This is what early access delivers — a pip-installable compiler that takes Python in and emits HDL out.

Horizon 2

The full toolchain

Import existing VHDL, Verilog, and C++ into XiperLab projects. All sources compile to a shared intermediate representation for simulation and verification. Emit HDL from mixed-language designs. IDE integration with linting and language server support for VS Code.

Horizon 3

Collaborative hardware development

XiperLab in the browser. Edit designs collaboratively in real time. Stream simulation results as you type. Hardware development with the same workflow your team already uses for software.

Early access

Be among the first XiperPy developers.

Your feedback to the engineers shapes its evolution before it goes public later this year.

Join the team and build XiperPy with us.

Shape the software evolution in hardware engineering.

Find your role

VHDL. Verilog.Write Python.Generate hardware.