Principal Software Engineer, HDL Compiler

You will be the leading software engineer on the compiler, reporting to the CTO. You inherit the working prototype and architect the IR, the simulation engine, and the verification pipeline.

• Design and evolve the IR, likely multi-level (MLIR is one path), handling source semantics, hardware structure, and target-specific lowering
• Build the compiler: parsing, lowering, optimization passes, Verilog/VHDL code generation
• Build the simulation engine that runs mixed designs across Python, existing HDL, and C++ in a single run
• Build the verification pipeline: deterministic simulation testing, formal checks, synthesis regression against Vivado, Quartus, and Yosys

• Production experience building compilers, code generators, or EDA tooling
• Fluency in VHDL or Verilog and the FPGA development lifecycle
• Strong Python, including metaprogramming (metaclasses, descriptors, protocols)

• Python-to-HDL frameworks: Amaranth HDL, MyHDL, PyMTL3, Magma, cocotb
• LLVM or MLIR, particularly CIRCT or FIRRTL
• High-level synthesis: Google XLS, Vitis HLS, Catapult
• FPGA synthesis and place-and-route: Vivado, Quartus, Yosys, nextpnr
• Formal verification (SymbiYosys, JasperGold) or deterministic simulation testing

Company's mission is to enable teams to develop hardware designs at software speed.

We are building XiperPy, a software platform for hardware development. Engineers describe parallel hardware in Python and generate synthesizable HDL targeting FPGAs or ASICs. The platform provides a web-based development environment with real-time linting, unified simulation across XiperPy and existing HDL code, and output to VHDL or Verilog.

We have a working compiler prototype generating valid HDL from Python today. The CTO, Martin Heimlicher, founded Enclustra, Switzerland's leading FPGA design services and solutions company with 100+ employees and global distribution. He brings two decades of production FPGA and EDA experience to Company.

Company is seed-funded and headquartered in Zurich. The engineering team is planned to grow to 10 engineers through 2026.

• Shape the foundation. Join while the platform and compiler architecture are still taking shape. You will influence the compiler intermediate representation, the verification strategy, and the development environment.
• Hardware meets software. Your compiler output is validated on real FPGAs today.
• Founding-team equity. Early-stage compensation may include equity.