Principal Software Engineer, Platform UI
XiperPy's web IDE is where engineers write Python, read compiler diagnostics, run simulations, and visualize hardware structure. It needs an editor built on LSP that streams diagnostics from the compiler, local-first collaboration with offline support, and visualization that renders circuit topology and timing constraints at interactive frame rates. The IDE is the only surface engineers touch; if it is slow or fights them, the compiler underneath does not matter.
About the role
You will be the leading software engineer on the platform, reporting to the CTO. You architect the editor, the collaboration layer, and the hardware visualization.
Responsibilities
- Design the editor architecture: LSP integration with the compiler backend, state management, extensibility
- Build local-first collaboration: CRDT-based document sync, offline capability, conflict resolution
- Build hardware visualization: circuit topology, component placement, timing and constraint views
- Integrate simulation into the editor, streaming results from the compiler's mixed-language engine
Required qualifications
- Production experience building IDE-like or highly interactive web applications
- Performance engineering for data-intensive UIs: canvas rendering, virtualization, web workers
- Local-first or real-time collaborative editing architecture
Preferred qualifications
- LSP server or client implementation
- Monaco, CodeMirror, or VS Code extension development
- Incremental parsing (tree-sitter or similar)
- Data visualization for technical domains: circuit diagrams, floorplans, dependency graphs
- Familiarity with FPGA development workflows or EDA tool UX
About Company
Company's mission is to enable teams to develop hardware designs at software speed.
We are building XiperPy, a software platform for hardware development. Engineers describe parallel hardware in Python and generate synthesizable HDL targeting FPGAs or ASICs. The platform provides a web-based development environment with real-time linting, unified simulation across XiperPy and existing HDL code, and output to VHDL or Verilog.
We have a working compiler prototype generating valid HDL from Python today. The CTO, Martin Heimlicher, founded Enclustra, Switzerland's leading FPGA design services and solutions company with 100+ employees and global distribution. He brings two decades of production FPGA and EDA experience to Company.
Company is seed-funded and headquartered in Zurich. The engineering team is planned to grow to 10 engineers through 2026.
Why Company
- Shape the foundation. Join while the platform and compiler architecture are still taking shape. You will influence the compiler intermediate representation, the verification strategy, and the development environment.
- Hardware meets software. Your compiler output is validated on real FPGAs today.
- Founding-team equity. Early-stage compensation may include equity.
Interested?
Tell us what you would build at Xiper.