Staff Software Engineer, Python HDL Library
XiperPy ships a library of reusable hardware components. Each component is written in Python and must generate correct, synthesizable Verilog and VHDL. The job is building and verifying these components so that teams can assemble working designs without writing HDL by hand.
About the role
You write and verify hardware components in Python using the XiperPy framework.
Responsibilities
- Implement hardware components in Python using XiperPy
- Verify each component through simulation and synthesis
- Document component interfaces, timing constraints, and resource usage
- Surface framework bugs and API gaps to the compiler team
Required qualifications
- Python, including metaprogramming (metaclasses, descriptors, protocols)
- Fluency in VHDL or Verilog and the FPGA development lifecycle
- Hands-on FPGA development: synthesis, place-and-route, timing closure
Preferred qualifications
- Python verification frameworks: cocotb, PyMTL3, Amaranth HDL
- FPGA synthesis tools: Vivado, Quartus, Yosys
- DSP, crypto, or network protocol implementation in HDL
- Writing technical documentation for hardware IP
About Company
Company's mission is to enable teams to develop hardware designs at software speed.
We are building XiperPy, a software platform for hardware development. Engineers describe parallel hardware in Python and generate synthesizable HDL targeting FPGAs or ASICs. The platform provides a web-based development environment with real-time linting, unified simulation across XiperPy and existing HDL code, and output to VHDL or Verilog.
We have a working compiler prototype generating valid HDL from Python today. The CTO, Martin Heimlicher, founded Enclustra, Switzerland's leading FPGA design services and solutions company with 100+ employees and global distribution. He brings two decades of production FPGA and EDA experience to Company.
Company is seed-funded and headquartered in Zurich. The engineering team is planned to grow to 10 engineers through 2026.
Why Company
- Shape the foundation. Join while the platform and compiler architecture are still taking shape. You will influence the compiler intermediate representation, the verification strategy, and the development environment.
- Hardware meets software. Your compiler output is validated on real FPGAs today.
- Founding-team equity. Early-stage compensation may include equity.
Interested?
Tell us what you would build at Xiper.